typedef unsigned int size_t;
typedef int int32_t;
typedef unsigned char uint8_t;
typedef unsigned int uint32_t;
typedef unsigned long long uint64_t;
typedef uint32_t target_phys_addr_t;
struct QEMUFile;
typedef struct QEMUFile QEMUFile;
struct PCIBus;
typedef struct PCIBus PCIBus;
struct PCIDevice;
typedef struct PCIDevice PCIDevice;
struct IRQState;
typedef struct IRQState *qemu_irq;
struct DeviceState;
typedef struct DeviceState DeviceState;
struct Monitor;
struct Monitor;
typedef struct Monitor Monitor;
typedef int LoadStateHandler (QEMUFile * f, void *opaque, int version_id);
struct VMStateInfo;
typedef struct VMStateInfo VMStateInfo;
struct VMStateDescription;
typedef struct VMStateDescription VMStateDescription;
struct VMStateInfo
{
  char const *name;
  int (*get) (QEMUFile * f, void *pv, size_t size);
  void (*put) (QEMUFile * f, void *pv, size_t size);
};
enum VMStateFlags
{
  VMS_SINGLE = 1,
  VMS_POINTER = 2,
  VMS_ARRAY = 4,
  VMS_STRUCT = 8,
  VMS_VARRAY_INT32 = 16,
  VMS_BUFFER = 32,
  VMS_ARRAY_OF_POINTER = 64,
  VMS_VARRAY_UINT16 = 128,
  VMS_VBUFFER = 256,
  VMS_MULTIPLY = 512
};
struct __anonstruct_VMStateField_76
{
  char const *name;
  size_t offset;
  size_t size;
  size_t start;
  int num;
  size_t num_offset;
  size_t size_offset;
  VMStateInfo const *info;
  enum VMStateFlags flags;
  VMStateDescription const *vmsd;
  int version_id;
    _Bool (*field_exists) (void *opaque, int version_id);
};
typedef struct __anonstruct_VMStateField_76 VMStateField;
struct VMStateDescription
{
  char const *name;
  int version_id;
  int minimum_version_id;
  int minimum_version_id_old;
  LoadStateHandler *load_state_old;
  int (*pre_load) (void *opaque);
  int (*post_load) (void *opaque, int version_id);
  void (*pre_save) (void *opaque);
  void (*post_save) (void *opaque);
  VMStateField *fields;
};
struct QemuOpts;
typedef struct QemuOpts QemuOpts;
struct Property;
typedef struct Property Property;
struct PropertyInfo;
typedef struct PropertyInfo PropertyInfo;
struct DeviceInfo;
typedef struct DeviceInfo DeviceInfo;
struct BusState;
typedef struct BusState BusState;
struct BusInfo;
typedef struct BusInfo BusInfo;
enum DevState
{
  DEV_STATE_CREATED = 1,
  DEV_STATE_INITIALIZED = 2
};
struct __anonstruct_child_bus_89
{
  struct BusState *lh_first;
};
struct __anonstruct_sibling_90
{
  struct DeviceState *le_next;
  struct DeviceState **le_prev;
};
struct DeviceState
{
  char const *id;
  enum DevState state;
  QemuOpts *opts;
  int hotplugged;
  DeviceInfo *info;
  BusState *parent_bus;
  int num_gpio_out;
  qemu_irq *gpio_out;
  int num_gpio_in;
  qemu_irq *gpio_in;
  struct __anonstruct_child_bus_89 child_bus;
  int num_child_bus;
  struct __anonstruct_sibling_90 sibling;
};
struct BusInfo
{
  char const *name;
  size_t size;
  void (*print_dev) (Monitor * mon, DeviceState * dev, int indent);
  Property *props;
};
struct __anonstruct_children_91
{
  struct DeviceState *lh_first;
};
struct __anonstruct_sibling_92
{
  struct BusState *le_next;
  struct BusState **le_prev;
};
struct BusState
{
  DeviceState *parent;
  BusInfo *info;
  char const *name;
  int allow_hotplug;
  int qdev_allocated;
  struct __anonstruct_children_91 children;
  struct __anonstruct_sibling_92 sibling;
};
struct Property
{
  char const *name;
  PropertyInfo *info;
  int offset;
  void *defval;
};
enum PropertyType
{
  PROP_TYPE_UNSPEC = 0,
  PROP_TYPE_UINT8 = 1,
  PROP_TYPE_UINT16 = 2,
  PROP_TYPE_UINT32 = 3,
  PROP_TYPE_INT32 = 4,
  PROP_TYPE_UINT64 = 5,
  PROP_TYPE_TADDR = 6,
  PROP_TYPE_MACADDR = 7,
  PROP_TYPE_DRIVE = 8,
  PROP_TYPE_CHR = 9,
  PROP_TYPE_STRING = 10,
  PROP_TYPE_NETDEV = 11,
  PROP_TYPE_VLAN = 12,
  PROP_TYPE_PTR = 13
};
struct PropertyInfo
{
  char const *name;
  size_t size;
  enum PropertyType type;
  int (*parse) (DeviceState * dev, Property * prop, char const *str);
  int (*print) (DeviceState * dev, Property * prop, char *dest, size_t len);
};
struct DeviceInfo
{
  char const *name;
  char const *alias;
  char const *desc;
  size_t size;
  Property *props;
  int no_user;
  void (*reset) (DeviceState * dev);
  VMStateDescription const *vmsd;
  int (*init) (DeviceState * dev, DeviceInfo * info);
  int (*unplug) (DeviceState * dev);
  int (*exit) (DeviceState * dev);
  BusInfo *bus_info;
  struct DeviceInfo *next;
};
typedef uint64_t pcibus_t;
typedef void PCIConfigWriteFunc (PCIDevice * pci_dev, uint32_t address,
				 uint32_t data, int len);
typedef uint32_t PCIConfigReadFunc (PCIDevice * pci_dev, uint32_t address,
				    int len);
typedef void PCIMapIORegionFunc (PCIDevice * pci_dev, int region_num,
				 pcibus_t addr, pcibus_t size, int type);
struct PCIIORegion
{
  pcibus_t addr;
  pcibus_t size;
  pcibus_t filtered_size;
  uint8_t type;
  PCIMapIORegionFunc *map_func;
};
typedef struct PCIIORegion PCIIORegion;
struct PCIDevice
{
  DeviceState qdev;
  uint8_t *config;
  uint8_t *cmask;
  uint8_t *wmask;
  uint8_t *used;
  PCIBus *bus;
  uint32_t devfn;
  char name[64];
  PCIIORegion io_regions[7];
  PCIConfigReadFunc *config_read;
  PCIConfigWriteFunc *config_write;
  qemu_irq *irq;
  int irq_state[4];
  uint32_t cap_present;
  uint8_t msix_cap;
  int msix_entries_nr;
  uint8_t *msix_table_page;
  int msix_mmio_index;
  unsigned int *msix_entry_used;
  uint32_t msix_bar_size;
  int32_t version_id;
};
struct __anonstruct_SHPCIC_97
{
  PCIBus *bus;
  PCIDevice *dev;
  uint32_t par;
  uint32_t mbr;
  uint32_t iobr;
};
typedef struct __anonstruct_SHPCIC_97 SHPCIC;
void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val);
extern void pci_data_write (PCIBus * s, uint32_t addr, uint32_t val, int len);
void
sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val)
{
  uint32_t *__tmp__282;

  switch ((int) addr)
    {
    case 0:
    case 1:
    case 2:
    case 3:
    case 4:
    case 5:
    case 6:
    case 7:
    case 8:
    case 9:
    case 10:
    case 11:
    case 12:
    case 13:
    case 14:
    case 15:
    case 16:
    case 17:
    case 18:
    case 19:
    case 20:
    case 21:
    case 22:
    case 23:
    case 24:
    case 25:
    case 26:
    case 27:
    case 28:
    case 29:
    case 30:
    case 31:
    case 32:
    case 33:
    case 34:
    case 35:
    case 36:
    case 37:
    case 38:
    case 39:
    case 40:
    case 41:
    case 42:
    case 43:
    case 44:
    case 45:
    case 46:
    case 47:
    case 48:
    case 49:
    case 50:
    case 51:
    case 52:
    case 53:
    case 54:
    case 55:
    case 56:
    case 57:
    case 58:
    case 59:
    case 60:
    case 61:
    case 62:
    case 63:
    case 64:
    case 65:
    case 66:
    case 67:
    case 68:
    case 69:
    case 70:
    case 71:
    case 72:
    case 73:
    case 74:
    case 75:
    case 76:
    case 77:
    case 78:
    case 79:
    case 80:
    case 81:
    case 82:
    case 83:
    case 84:
    case 85:
    case 86:
    case 87:
    case 88:
    case 89:
    case 90:
    case 91:
    case 92:
    case 93:
    case 94:
    case 95:
    case 96:
    case 97:
    case 98:
    case 99:
    case 100:
    case 101:
    case 102:
    case 103:
    case 104:
    case 105:
    case 106:
    case 107:
    case 108:
    case 109:
    case 110:
    case 111:
    case 112:
    case 113:
    case 114:
    case 115:
    case 116:
    case 117:
    case 118:
    case 119:
    case 120:
    case 121:
    case 122:
    case 123:
    case 124:
    case 125:
    case 126:
    case 127:
    case 128:
    case 129:
    case 130:
    case 131:
    case 132:
    case 133:
    case 134:
    case 135:
    case 136:
    case 137:
    case 138:
    case 139:
    case 140:
    case 141:
    case 142:
    case 143:
    case 144:
    case 145:
    case 146:
    case 147:
    case 148:
    case 149:
    case 150:
    case 151:
    case 152:
    case 153:
    case 154:
    case 155:
    case 156:
    case 157:
    case 158:
    case 159:
    case 160:
    case 161:
    case 162:
    case 163:
    case 164:
    case 165:
    case 166:
    case 167:
    case 168:
    case 169:
    case 170:
    case 171:
    case 172:
    case 173:
    case 174:
    case 175:
    case 176:
    case 177:
    case 178:
    case 179:
    case 180:
    case 181:
    case 182:
    case 183:
    case 184:
    case 185:
    case 186:
    case 187:
    case 188:
    case 189:
    case 190:
    case 191:
    case 192:
    case 193:
    case 194:
    case 195:
    case 196:
    case 197:
    case 198:
    case 199:
    case 200:
    case 201:
    case 202:
    case 203:
    case 204:
    case 205:
    case 206:
    case 207:
    case 208:
    case 209:
    case 210:
    case 211:
    case 212:
    case 213:
    case 214:
    case 215:
    case 216:
    case 217:
    case 218:
    case 219:
    case 220:
    case 221:
    case 222:
    case 223:
    case 224:
    case 225:
    case 226:
    case 227:
    case 228:
    case 229:
    case 230:
    case 231:
    case 232:
    case 233:
    case 234:
    case 235:
    case 236:
    case 237:
    case 238:
    case 239:
    case 240:
    case 241:
    case 242:
    case 243:
    case 244:
    case 245:
    case 246:
    case 247:
    case 248:
    case 249:
    case 250:
    case 251:
    case 252:;
      __tmp__282 = (uint32_t *) ((((SHPCIC *) p)->dev)->config + addr);
      *__tmp__282 = val;
      break;
    case 448:;
      ((SHPCIC *) p)->par = val;
      break;
    case 452:;
      ((SHPCIC *) p)->mbr = val;
      break;
    case 456:;
      ((SHPCIC *) p)->iobr = val;
      break;
    case 544:;
      pci_data_write (((SHPCIC *) p)->bus, ((SHPCIC *) p)->par, val, 4);
      break;
    }
  return;
}

/* Checksum = E88C5111, Size = 299, Name = /home/regehr/z/qemu-0.12.0-rc1/sh4-softmmu/sh_pci.i */
/* Original File = /home/regehr/z/qemu-0.12.0-rc1/hw/sh_pci.c, At line = 39 */